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Using Model Checking in a Parallelizing Compiler

Date of Publication: 
January 1998
Associated Research Groups: 
In this paper we describe the usage of temporal logic model checking in a parallelizing compiler to analyze the structure of a source program and locate opportunities for optimization and parallelization. The source program is represented as a process graph in which the nodes are sequential processes and the edges are control and data dependence relationships between the computations at the nodes. By labeling the nodes and edges with descriptive atomic propositions and by specifying the conditions necessary for optimizations and parallelizations as temporal logic formulas, we can use a model checker to locate nodes of the process graph where particular optimizations can be made. To discover opportunities for new optimizations or modify existing ones in this parallelizing compiler, we need only specify their conditions as temporal logic formulas; we do not need to add to or modify the code of the compiler. This greatly simplifies the process of locating optimization and parallelization opportunities in the source program and makes it easier to experiment with complex optimizations. Hence, this methodology provides a convenient, concise, and formal framework in which to carry out program optimizations by compilers.
Parallel Processing Letters. in Volume 8, Number 4
@article{Eric98a, author = "Rus, T. and Van Wyk, E.", title = "Using Model Checking in a Parallelizing Compiler", journal = "Parallel Processing Letters", year = 1998, volume = 8, number = 4, pages = "459--471" }